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Chapter Review

In this chapter, we have begun our study of circuits with state by looking at the fundamental building block of such circuits: the latch and its more complex derivative, the flip-flop. We introduced the basic R-S latch and the level-sensitive R-S latch. These devices suffer from a "forbidden state." Once this state is entered, the state you will go to next is -unpredictable.

The J-K flip-flop attempts to eliminate the forbidden state, replacing it with an ability to toggle the state instead. However, simply feeding the outputs back to the inputs of a J-K flip-flop is not sufficient to correct the problem, and we introduce an alternative implementation approach, called the master/slave flip-flop. The flip-flop is constructed from two stages of latches, the first being set while the clock is high, the second when the clock goes low. This "two-phase" approach breaks any possible feedback paths. But master/slave flip-flops have their own problem: ones catching. We correct this problem in positive and negative edge-triggered flip-flops.

Next we discussed some issues related to clock methodologies, starting with the meaning of setup and hold time constraints as they relate to latches and flip-flops. If an input changes within the window formed by the setup time before the clocking event and the hold time after the clocking event, we do not know what value will be stored in the memory element. There is even a chance that the flip-flop will be caught in an in-between state, called the metastable state, should the input change too near the clock edge. Theoretically, it could be stuck in this state forever. Fortunately, when a system is constructed from a compatible family of logic, such as TTL LS logic, flip-flops can be cascaded without fear of setup and hold time violations.

We also described narrow-width clocking and two-phase nonoverlapped clocking, which are methodologies needed when building systems from latches. The two-phase clocking scheme, commonly used in some variation within VLSI systems, has the advantage that you need only worry about worst-case signal propagation delays. Narrow-width clocking has the disadvantage that you must also be concerned with "fast signals." This requires a careful analysis of best-case propagation delays as well as worst-case ones. Neither approach is necessary if edge-triggered flip-flops are used, since clock edges rather than levels are used to control state updates in the storage elements.

Finally, we briefly described asynchronous inputs and the dangers in using them. Unfortunately, they cannot be completely eliminated. We introduced the synchronizer concept to reduce their danger. We also showed the four-cycle signaling convention as a protocol for communication among independently clocked subsystems. We presented the concept of a self-timed circuit, which determines on it own when it has finished computing its function. These circuits will provide the basis for future systems that may have no clocks in them at all.

Further Reading

Most logic design textbooks provide an extensive discussion of flip-flops along the lines of the presentation we have given here. However, clocking issues and metastability are not usually covered as thoroughly. An unusual exception to this is T. R. Blakeslee's book, Digital Design with Standard MSI & LSI, 2nd edition, Wiley, New York, 1979. Chapter 6, "Nasty Realities I: Race Conditions and Hang-up States," formed the basis for our discussion of asynchronous inputs, clock skew, and metastable states.

The concept of narrow-width versus two-phase nonoverlapped clocking is best described in C. Mead and L. Conway's classic text Introduction to VLSI Design, Addison-Wesley, Reading, MA, 1980. Chapter 7, "System Timing," contributed by Professor C. Seitz of the California Institute of Technology, provided the motivation for the discussion of clocking strategies, metastable behavior, and self-timed circuits in this chapter. Although it is an advanced presentation, it should be read by every designer attempting to build a high-performance system.

Metastability has plagued digital designers for many years but was not well understood until the mid-1970s. The classic papers describing the phenomenon include Chaney, Ornstein, and Littlefield, "Beware the Synchronizer," Proceedings of the Spring COMPCON Meeting, San Francisco, September 1972, and Chaney and Molnar, "Anomalous Behavior of Synchronizer and Arbiter Circuits," IEEE Transactions on Computers, C-22:4, 421-422 (April 1973).

The concepts of self-timed circuits date back to the early days of computers, but the increased difficulty of building such systems has limited their application in digital design. Self-timed concepts, however, are used extensively in advanced dynamic memory components. The best place to start in finding out more about self-timed circuits is in Seitz's chapter in Mead and Conway's book referenced above. A research group, led by Professor Alain Martin of the California Institute of Technology, has succeeded in implementing a complete 32-bit microprocessor using self-timed techniques. Their work is reported in the 10th CALTECH Conference VLSI Proceedings; the conference was held in March 1989 in Pasadena, CA.

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This file last updated on 07/14/96 at 15:33:06.
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